module top_module (
    input clk,
    input reset,
    output [9:0] q);

    //reg	[9:0]	cnt;
    
    always @(posedge clk)
        begin
            if(reset)
                begin
                    q <= 10'd0;
                end
            else
                begin
                    if(q == 10'd999)
                        begin
                            q <= 10'd0;
                        end
                    else
                        begin
                            q <= q + 1'b1;
                        end
                end
        end
    
endmodule
